The present disclosure relates to the formation of semiconductor devices. More specifically, the disclosure relates to the formation of stair-step semiconductor devices.
During semiconductor wafer processing, stair-step features are sometimes required. For example, in 3D flash memory devices, multiple cells are stacked up together in chain format to save space and increase packing density. The stair-step structure allows electrical contact with every gate layer.
U.S. Pat. No. 8,535,549, by Fu et al. issued on Sep. 17, 2013, which is incorporated by reference for all purposes, discloses the deposition of a hardmask over an organic mask in forming a stair-step structure.